WM8985
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
PLLK[8:0]
DEFAULT
DESCRIPTION
REFER TO
39 (27h)
8:0
011101001
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Master Clock
and Phase
Locked Loop
(PLL)
41 (29h)
8:4
3:0
00000
0000
Reserved. Initialise to 0
Stereo depth
DEPTH3D
3D Stereo
Enhancement
0000: 0% (minimum 3D effect)
0001: 6.67%
....
1110: 93.3%
1111: 100% (maximum 3D effect)
Controls the OUT4 to ADC input boost stage:
000 = Path disabled (disconnected)
001 = -12dB gain
42 (2Ah)
8:6
OUT4_2ADCVOL
000
Analogue
Outputs
010 = -9dB gain
011 = -6dB gain
100 = -3dB gain
101 = +0dB gain
110 = +3dB gain
111 = +6dB gain
5
OUT4_2LNR
0
OUT4 to L or R ADC input
0 = Right ADC input
1 = Left ADC input
Analogue
Outputs
4:0
8
0 0000
0
Reserved. Initialise to 0
43 (2Bh)
BYPL2RMIX
BYPR2LMIX
Left bypass path (from the Left channel input
PGA stage) to right output mixer
Analogue
Outputs
0 = not selected
1 = selected
7
0
Right bypass path (from the right channel input
PGA stage) to Left output mixer
Analogue
Outputs
0 = not selected
1 = selected
6
5
0
0
Reserved. Initialise to 0
Mute input to INVROUT2 mixer
MUTERPGA2INV
INVROUT2
Analogue
Outputs
4
0
Mute input to INVROUT2 mixer
Analogue
Outputs
3:1
BEEPVOL
000
AUXR input to ROUT2 inverter gain
000 = -15dB
Analogue
Outputs
...
111 = +6dB
0
8
BEEPEN
MBVSEL
0
0
0 = mute AUXR beep input
1 = enable AUXR beep input
Microphone Bias Voltage Control
0 = 0.9 * AVDD
Analogue
Outputs
44 (2Ch)
Input Signal
Path
1 = 0.65 * AVDD
7
6
0
0
Reserved. Initialise to 0
R2_2INPPGA
Connect R2 pin to right channel input PGA
positive terminal.
Input Signal
Path
0=R2 not connected to input PGA
1=R2 connected to input PGA amplifier positive
terminal (constant input impedance).
PP, Rev 3.4, October 2006
102
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
