Pre-Production
WM8985
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Per step
Per 6dB
726.4us
1.453ms
2.905ms
90% of range
5.26ms
0000
0001
0010
90.8us
181.6us
363.2us
10.53ms
21.06ms
… (time doubles with every step)
1010 93ms 744ms
5.39s
3:0
ALCATK
0010
ALC attack (gain ramp-down) time
(ALCMODE == 0)
Input Limiter/
Automatic
Level Control
(ALC)
Per step
104us
208us
416us
Per 6dB
832us
90% of range
6ms
0000
0001
0010
1.664ms
3.328ms
12ms
24.1ms
… (time doubles with every step)
1010
or
106ms
852ms
6.18s
higher
0010
ALC attack (gain ramp-down) time
(ALCMODE == 1)
Per step
22.7us
45.4us
90.8us
Per 6dB
182.4us
363.2us
726.4us
90% of range
1.31ms
0000
0001
0010
2.62ms
5.26ms
… (time doubles with every step)
1010 23.2ms 186ms
1.348s
35 (23h)
8:4
3
00000
0
Reserved. Initialise to 0
ALC Noise gate function enable
1 = enable
NGEN
NGTH
Input Limiter/
Automatic
Level Control
(ALC)
0 = disable
2:0
000
ALC Noise gate threshold:
000=-39dB
Input Limiter/
Automatic
Level Control
(ALC)
001=-45dB
010=-51db
… (6dB steps)
111=-81dB
36 (24h)
8:5
4
0000
0
Reserved. Initialise to 0
PLLPRESCALE
PLLN[3:0]
0 = MCLK input not divided (default)
Master Clock
and Phase
Locked Loop
(PLL)
1 = Divide MCLK by 2 before input to PLL
3:0
1000
Integer (N) part of PLL input/output frequency
ratio. Use values greater than 5 and less than
13.
Master Clock
and Phase
Locked Loop
(PLL)
37 (25h)
38 (26h)
8:6
5:0
000
Reserved. Initialise to 0
PLLK[23:18]
PLLK[17:9]
01100
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Master Clock
and Phase
Locked Loop
(PLL)
8:0
010010011
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Master Clock
and Phase
Locked Loop
(PLL)
PP, Rev 3.4, October 2006
101
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
