WM8961
Pre-Production
The default values of the write control sequencer are given in Table 50
WM8961
REG
WSEQ
CUMULATIVE STARTUP
_LOCATION _INDEX
EOS
1’b0
WIDTH START DATA
DELAY
COMMENT
DELAY
TIME
0
1
8’h08
8’hFE
3’h0
3’h0
4’h4
4’h0
8’h1
8’h0
4’h0
CLK_DSP_ENA = 1
Dummy Write for
expansion
BUFDCOPEN = 1,
BUFIOEN = 1 ; Enable
current bias circuits
VMIDSEL = 01, VREF
= 1 ; VMID can be
brought up fast,
0.0005
0.0005
1’b0
1’b0
4’h0
4’h0
0.0005
0.0005
0.0010
0.0015
2
8’h1C
3’h1
4’h3
8’h3
3
4
8’h19
8’h48
1’b0
1’b0
3’h2
3’h0
4’h6
4’h0
8’h3
4’h0
4’h6
master bias enable
Enable Charge pump,
wait 4.5ms
0.0005
0.0045
0.0020
0.0065
8’h01
LOUT1_PGA = 1,
ROUT1_PGA = 1,
DACL = 1, DACR = 1
Set HPL_ENA,
HPR_ENA
Set HPL_EN_DLY,
HPR_EN_DLY
5
6
7
8
8’h1A
8’h45
8’h45
8’h02
1’b0
1’b0
1’b0
1’b0
3’h3
3’h4
3’h4
3’h6
4’h5
4’h0
4’h1
4’h0
8’hF
4’h0
4’h0
4’h0
4’h0
0.0005
0.0005
0.0005
0.0005
0.0070
0.0075
0.0080
0.0085
8’h11
8’h19
8’h65
LOUT1VOL to -20dB
(7’b1100101)
ROUT1VOL to -20dB
(7’b1100101)
9
8’h03
8’h03
1’b0
1’b0
3’h6
3’h0
4’h0
4’h8
8’h65
8’h01
4’h0
4’h0
0.0005
0.0005
0.0090
0.0095
10
OUT1VU
Enable Servo on
outputs, trigger
startup, wait 256ms
Dummy Write for
expansion
11
8’h3D
1’b0
3’h5
4’h2
8’h33
4’hC
0.2560
0.2655
12
13
8’hFE
8’h07
1’b0
1’b0
3’h0
3’h1
4’h0
4’h2
8’h0
8’h0
4’h0
4’h0
0.0005
0.0005
0.2660
0.2665
AIF WL = 16 bit
Set HPL_ENA_OUTP
& HPR_ENA_OUTP
14
8’h45
1’b0
3’h4
4’h2
8’h1D
4’h0
0.0005
0.2670
Set HPL_RMV_SHRT
& HPR_RMV_SHRT
Dummy Write for
expansion
15
16
8’h45
8’hFE
1’b0
1’b0
3’h4
3’h0
4’h3
4’h0
8’h1F
8’h0
4’h0
4’h0
0.0005
0.0005
0.2675
0.2680
DAC Soft unmute, wait
16.5ms
17
18
19
8’h5
1’b1
1’b0
1’b0
3’h0
3’h1
3’h1
4’h3
4’h4
4’h4
8’h0
4’h8
4’h0
4’h0
0.0165
0.0005
0.0005
0.2845
0.0005
0.0010
8’h20
8’h21
8’h03
8’h03
LMICBOOST = 11
RMICBOOST = 11
AINL = 1, AINR = 1,
MICB = 1
Enable Servo on
inputs, trigger startup,
wait 256ms
20
21
8’h19
8’h3C
1’b0
1’b0
3’h4
3’h5
4’h1
4’h2
8’h19
8’h33
4’h0
4’hC
0.0005
0.2560
0.0015
0.2575
Dummy Write for
expansion
22
23
24
25
8’hFE
8’h19
8’h20
8’h21
1’b0
1’b0
1’b0
1’b0
3’h0
3’h1
3’h1
3’h1
4’h0
4’h2
4’h4
4’h4
8’h00
8’h3
8’h0
8’h0
4’h0
4’h0
4’h0
4’h0
0.0005
0.0005
0.0005
0.0005
0.2580
0.2585
0.2590
0.2595
ADCL = 1, ADCR = 1
LMICBOOST = 00
RMICBOOST = 00
Dummy Write for
expansion
26
8’hFE
1’b1
3’h0
4’h0
8’h00
4’h0
0.0005
0.2600
DAC Soft mute, wait
16.5ms
27
28
29
8’h5
1’b0
1’b0
1’b0
3’h0
3’h0
3’h1
4’h3
4’h7
4’h7
8’h1
4’h8
4’h0
4’h0
0.0165
0.0005
0.0005
0.0165
0.0170
0.0175
8’h00
8’h01
8’h01
8’h03
LINMUTE = 1
RINMUTE = 1, IPVU
PP, August 2009, Rev 3.1
w
67
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
