WM8961
Pre-Production
DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
3:0
ATK
[3:0]
0010
(24ms)
ALC attack (gain ramp-down) time
0000 = 6ms
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
R27 (1Bh)
Additional
Control (3)
2:0
SAMPLE_RATE[2:0]
000
ALC Sample Rate
000 = 44.1k / 48k
001 = 32k
010 = 22.05k / 24k
011 = 16k
100 = 11.25k / 12k
101 = 8k
110 and 111 = Reserved
Table 15 ALC Control
ALC SAMPLE RATE CONTROL
The register bits R27[2:0],SAMPLE_RATE must be set correctly to ensure that the ALC attack, decay
and hold times are correct for the chosen sample rate as shown in Table 15.
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped
down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full
scale. This function is automatically enabled whenever the ALC is enabled.
Note:
If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to
prevent clipping when long attack times are used.
PP, August 2009, Rev 3.1
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
