WM8961
Pre-Production
CONTROL INTERFACE TIMING
The WM8961 is controlled via a 2-wire serial control interface.
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t9
Figure 4 2-Wire Serial Control Interface Timing
Test Conditions
MICVDD=2.5V, DVDD = CPVDD=AVDD =1.8V SPKVDD1 = SPKVDD2 = 5V,
DGND=AGND=CPGND=SPKGND1=SPKGND2=0V,
TA=+25oC, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK Frequency
SYMBOL
MIN
TYP
MAX
UNIT
526
kHz
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulse-Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
1.3
600
600
600
100
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDIN, SCLK Rise Time
300
300
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
600
0
900
5
Pulse width of spikes that will be suppressed
Note:
Device Address = 0x94.
PP, August 2009, Rev 3.1
w
16
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
