Production Data
WM8945
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R65 (41h)
SE1_LHPF_
CONFIG
SE1_LHPF_L
_ENA
SE1 Left channel low-pass / high-
pass filter enable
0
0
0 = Disabled
1 = Enabled
R71 (47h)
SE1_NOTCH_L_
ENA
SE1 Left channel notch filters
enable
0
0
0
0
SE1_NOTCH_
CONFIG
0 = Disabled
1 = Enabled
R92 (5Ch)
SE1_DF1_
CONFIG
SE1_DF1_L
_ENA
SE1 Left channel DF1 filter enable
0 = Disabled
1 = Enabled
Table 13 Signal Enhancement Block 1 (SE1)
The SE2 ‘enable’ bits are described in Table 14. Note that (with the exception of the SE2 HPF) other
control fields must also be determined and written to the WM8945 using WISCE™ or other tools. The
registers described below only allow the sub-blocks of SE2 to be enabled or disabled.
Note that it is not recommended to access these control fields unless appropriate values have been
written to the associated bits in registers R99 to R175.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R100 (64h)
SE2_RETUNE_
L_ENA
SE2 Left channel ReTune™ filter
enable
0
0
SE2_RETUNE
_CONFIG
0 = Disabled
1 = Enabled
R133 (85h)
SE2_5BEQ_
CONFIG
SE2_5BEQ_L
_ENA
SE2 Left channel 5-band EQ enable
0 = Disabled
0
0
1 = Enabled
Table 14 Signal Enhancement Block 2 (SE2)
The register controls for Signal Enhancement Block SE3 are defined in the “Dynamic Range Control
(DRC)” section.
DYNAMIC RANGE CONTROL (DRC)
The dynamic range controller (DRC) is a circuit which can be enabled in the digital playback or digital
record path of the WM8945, depending upon the selected DSP mode. The function of the DRC is to
adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range,
e.g. when recording from microphones built into a handheld system.
The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-
clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the
presence of loud impulsive noises.
The DRC also incorporates a Noise Gate function, which provides additional attenuation of very low-
level input signals. This means that the signal path is quiet when no signal is present, giving an
improvement in background noise level under these conditions.
The DRC is enabled as described in Table 15. The audio signal path controlled by the DRC depends
upon the selected DSP Configuration mode – see “DSP Core” for details.
To remove any dc offsets from the input signal the ADC high pass filter must be enabled. The DRC
will not function correctly unless this filter is enabled.
Note that the ADC HPF bit in register R26(1Ah) bit 0 is NOT enabled by default but MUST be used if
DRC_ENA is enabled in register R29(1Dh) bit 7.
PD, May 2011, Rev 4.1
37
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
