Pre-Production
WM8940
Figure 10 ADC Digital Filter Path
The ADC is enabled by the ADCEN register bit.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2
0
ADCEN
0
0 = ADC disabled
1 = ADC enabled
Power
management 2
Table 11 ADC Enable
The polarity of the output signal can also be changed under software control using the ADCPOL
register bit.
REGISTER
ADDRESS
BIT
LABEL
ADCPOL
DEFAULT
DESCRIPTION
R14
ADC Control
Table 12 ADC Polarity
0
0
0=normal
1=inverted
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two
modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off
frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off
frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown
in Table 14.
REGISTER
ADDRESS
BIT
LABEL
HPFEN
DEFAULT
DESCRIPTION
R14
ADC Control
8
7
1
High Pass Filter Enable
0=disabled
1=enabled
HPFAPP
HPFCUT
0
Select audio mode or application mode
0=Audio mode (1st order, fc = ~3.7Hz)
1=Application mode (2nd order, fc =
HPFCUT)
6:4
000
Application mode cut-off frequency
See Table 14 for details.
Table 13 ADC Filter Select
Pre-Production, Rev 3.0, February 2007
23
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
