WM8912
Production Data
BCLK AND LRCLK CONTROL
The audio interface can be programmed to operate in master mode or slave mode using the
BCLK_DIR and LRCLK_DIR register bits. In master mode, the BCLK and LRCLK signals are
generated by the WM8912 when either of the DACs is enabled. In slave mode, the BCLK and
LRCLK clock outputs are disabled by default to allow another digital audio interface to drive these
pins.
It is also possible to force the BCLK or LRCLK signals to be output using BCLK_DIR and
LRCLK_DIR, allowing mixed master and slave modes. The BCLK_DIR and LRCLK_DIR fields are
defined in Table 35.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R25 (19h)
6
BCLK_DIR
0
Audio Interface BCLK Direction
0 = BCLK is input
Audio
Interface 1
1 = BCLK is output
R26 (1Ah)
4:0
BCLK_DIV
[4:0]
0_0100
BCLK Frequency (Master Mode)
00000 = SYSCLK
Audio
Interface 2
00001 = SYSCLK / 1.5
00010 = SYSCLK / 2
00011 = SYSCLK / 3
00100 = SYSCLK / 4
00101 = SYSCLK / 5
00110 = SYSCLK / 5.5
00111 = SYSCLK / 6
01000 = SYSCLK / 8 (default)
01001 = SYSCLK / 10
01010 = SYSCLK / 11
01011 = SYSCLK / 12
01100 = SYSCLK / 16
01101 = SYSCLK / 20
01110 = SYSCLK / 22
01111 = SYSCLK / 24
10000 = SYSCLK / 25
10001 = SYSCLK / 30
10010 = SYSCLK / 32
10011 = SYSCLK / 44
10100 = SYSCLK / 48
Audio Interface LRC Direction
0 = LRC is input
R27 (1Bh)
11
LRCLK_DIR
0
Audio
Interface 3
1 = LRC is output
10:0
LRCLK_RATE
[10:0]
000_0100
_0000
LRC Rate (Master Mode)
LRC clock output = BCLK / LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
Table 35 Digital Audio Interface Clock Control
PD, Rev 4.0, September 2010
60
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
