WM8912
Production Data
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
1 BCLK
1 BCLK
DACDAT
1
2
3
n-2
n-1
n
1
2
3
n-2
n-1
n
MSB
LSB
Input Word Length (WL)
Figure 32 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 33 and Figure
34. In device slave mode, Figure 35 and Figure 36, it is possible to use any length of frame pulse
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period
before the rising edge of the next frame pulse.
Figure 33 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)
Figure 34 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)
PD, Rev 4.0, September 2010
56
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
