Production Data
WM8912
DIGITAL AUDIO INTERFACE CONTROL
The register bits controlling audio data format, word length, left/right channel data source and TDM
are summarised in Table 33.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
5
AIFDACL_SR
C
0
Left DAC Data Source Select
0 = Left DAC outputs left channel data
1 = Left DAC outputs right channel data
Right DAC Data Source Select
0 = Right DAC outputs left channel data
1 = Right DAC outputs right channel data
DAC TDM Enable
Audio
Interface 0
4
13
12
7
AIFDACR_SR
C
1
0
0
0
0
R25 (19h)
AIFDAC_TDM
Audio
Interface 1
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
BCLK Invert
AIFDAC_TDM
_CHAN
AIF_BCLK_IN
V
0 = BCLK not inverted
1 = BCLK inverted
4
AIF_LRCLK_I
NV
LRC Polarity / DSP Mode A-B select.
Right, left and I2S modes – LRC polarity
0 = Not Inverted
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
3:2
1:0
AIF_WL [1:0]
AIF_FMT [1:0]
10
10
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Digital Audio Interface Format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = DSP
Table 33 Digital Audio Interface Data Control
AUDIO INTERFACE OUTPUT TRI-STATE
Register bit AIF_TRIS can be used to tri-state the audio interface pins as described in Table 34. All
digital audio interface pins will be tri-stated by this function, regardless of the state of other registers
which control these pin configurations.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R25 (19h)
8
AIF_TRIS
0
Audio Interface Tristate
Audio
Interface 1
0 = Audio interface pins operate normally
1 = Tristate all audio interface pins
Table 34 Digital Audio Interface Tri-State Control
PD, Rev 4.0, September 2010
59
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