Production Data
WM8912
AUDIO INTERFACE TIMING
MASTER MODE
BCLK
(output)
LRCLK
(output)
tDL
DACDAT
(input)
tDHT
tDST
Figure 2 Audio Interface Timing – Master Mode
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25oC, Master Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Interface Timing - Master Mode
LRCLK propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
20
ns
ns
ns
tDST
tDHT
20
10
PD, Rev 4.0, September 2010
15
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