WM8912
Production Data
SIGNAL TIMING REQUIREMENTS
COMMON TEST CONDITIONS
Unless otherwise stated, the following test conditions apply throughout the following sections:
•
•
•
•
Ambient temperature = +25°C
DCVDD = 1.0V
DBVDD = AVDD = CPVDD = 1.8V
DGND = AGND = CPGND = 0V
Additional, specific test conditions are given within the relevant sections below.
MASTER CLOCK
tMCLKY
MCLK
tMCLKL tMCLKH
Figure 1 Master Clock Timing
Master Clock Timing
PARAMETER
SYMBOL
TEST CONDITIONS
MCLK_DIV=1
MIN
40
TYP
MAX
UNIT
ns
TMCLKY
MCLK cycle time
MCLK duty cycle
MCLK_DIV=0
80
ns
TMCLKDS
60:40
40:60
PD, Rev 4.0, September 2010
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