Pre-Production
WM8904
MASTER AND SLAVE MODE OPERATION
The WM8904 digital audio interface can operate in master or slave mode, as shown in Figure 40 and
Figure 41.
Figure 40 Master Mode
Figure 41 Slave Mode
In master mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV.
In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE.
The BCLK input to this divider may be internal or external, allowing mixed master and slave modes.
The direction of these signals and the clock frequencies are controlled as described in the “Digital
Audio Interface Control” section.
BCLK and LRCLK can be enabled as outputs in Slave mode, allowing mixed Master/Slave operation -
see “Digital Audio Interface Control”.
OPERATION WITH TDM
Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same
bus. The WM8904 ADCs and DACs support TDM in master and slave modes for all data formats and
word lengths. TDM is enabled and configured using register bits defined in the “Digital Audio Interface
Control” section.
BCLK
BCLK
LRCLK
LRCLK
WM8904
Processor
WM8904
Processor
ADCDAT
DACDAT
ADCDAT
DACDAT
BCLK
BCLK
LRCLK
LRCLK
WM8904 or
Similar
WM8904 or
Similar
ADCDAT
DACDAT
ADCDAT
DACDAT
CODEC
CODEC
Figure 42 TDM with WM8904 as Master
Figure 43 TDM with Other CODEC as Master
PP, Rev 3.3, September 2012
91
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
