WM8802
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1/fs
LEFT
RIGHT
CHANNEL
CHANNEL
TLRCK (I)
TBCK (I)
TDATA (I)
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
16 to 24 bits
16 to 24 bits
Figure 26 Data Input Timing – Left Justified Data Input
VALIDITY FLAG INPUT (VI)
Validity flags can be input from RX5/VI by switching the RX5/VI input contents with VISEL.
The validity flag write timing is shown below. The validity flag can be written with the micro-controller
interface but port settings have priority.
Writing validity flags with the micro-controller interface is done using VMODE.
RX5/VI
OUTPUT CONDITIONS
0
No error
Error
1
Table 15 RX5/V1 Input
TLRCK
L1
R1
L2
R2
L3
TBCK
VI
V-L1
V-R1
V-L2
V-R2
V-L3
Internal latch signal
Figure 27 Validity Flag Input Timing
PP Rev 1.1 April 2004
34
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
