WM8802
Product Preview
REGISTER INPUT/OUTPUT
CONTENTS
CCB
ADDRESS
R/W
B0
B1
B2
B3
A0
A1
A2
A3
Function setting data input
CS data input
write
write
read
read
read
read
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Interrupt data output
fs data output
CS data output
Pc data output
Table 17 Relationship between Register Input/Output Contents and CCB Addresses
DATA WRITE METHOD
Input is performed in the following sequence: CCB addresses of A0 to A3 and B0 to B3, chip
addresses of DI0 and DI1, command addresses of DI4 to DI7 and data of DI8 to DI15. DI2 and DI3
are reserved for the system and should always be set to "0".
For the chip addresses, DI0 corresponds to CAL (low-order) and DI1 corresponds to CAU (high-
order).
DATA READ METHOD
Read data is output from DO. DO is in the high impedance state when CE is Low and begins
outputting at the rising edge of CE after the register address is recognised. DO then returns to the
high impedance state at the falling edge of CE.
If DO outputs using multiple WM8802 units are to be shared the DO outputs of the WM8802 can be
set to in a high impedance state using DOEN, This will prevent any misreading of registers from an
unselected device.
INPUT/OUTPUT TIMINGS
CE
CL
DI
….
B0 B1 B2 B3 A0 A1 A2 A3
DI0
DI1 DI2 DI3 DI4 DI5
DI15
DO
Hi-Z
Figure 30 Input Timing Chart (Normal, Low Clock)
PP Rev 1.1 April 2004
38
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
