Pre-Production
WM8786
In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 18 I2S Justified Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on the 2nd rising edge of BCLK following a
rising edge of LRC. Right channel data immediately follows left channel data. Depending on word
length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the
right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 19. In device
slave mode, Figure 20 it is possible to use any length of frame pulse less than 1/fs, providing the
falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the
next frame pulse.
Figure 19 DSP/PCM Mode Audio Interface (mode A, Master)
Figure 20 DSP/PCM Mode Audio Interface (mode A, Slave)
PP Rev 3.0 December 2005
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
