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WM8775
tBCH
tBCL
BCLK
ADCLRC
DOUT
tBCY
tDD
tLRSU
tLRH
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
ADCLRC set-up time to
BCLK rising edge
tLRSU
ADCLRC hold time from
BCLK rising edge
tLRH
tDD
10
0
ns
ns
DOUT propagation delay
from BCLK falling edge
10
Table 3 Digital Audio Data Timing – Slave Mode
Note:
ADCLRC should be synchronous with MCLK, although the WM8775 interface is tolerant of phase variations or jitter on
these signals.
PP Rev 1.8, June 2004
9
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
