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WM8775SEDS 参数 Datasheet PDF下载

WM8775SEDS图片预览
型号: WM8775SEDS
PDF下载: 下载PDF文件 查看货源
内容描述: 带4通道I / P多路复用器24位96 kHz的ADC [24 BIT 96 KHZ ADC WITH 4 CHANNEL I/P MULTIPLEXER]
分类和应用: 复用器
文件页数/大小: 36 页 / 346 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Product Preview  
WM8775  
TERMINOLOGY  
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output  
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).  
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.  
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB  
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).  
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.  
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).  
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from  
the other. Normally measured by sending a full scale signal down one channel and measuring the other.  
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.  
MASTER CLOCK TIMING  
tMCLKL  
MCLK  
tMCLKH  
tMCLKY  
Figure 1 Master Clock Timing Requirements  
Test Conditions  
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
MCLK System clock pulse width high  
MCLK System clock pulse width low  
MCLK System clock cycle time  
MCLK Duty cycle  
tMCLKH  
tMCLKL  
tMCLKY  
11  
11  
ns  
ns  
ns  
28  
40:60  
60:40  
Table 1 Master Clock Timing Requirements  
DIGITAL AUDIO INTERFACE – MASTER MODE  
BCLK  
DVD  
Controller  
WM8775  
ADC  
ADCLRC  
DOUT  
Figure 2 Audio Interface - Master Mode  
PP Rev 1.8, June 2004  
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