WM8775
Product Preview
Attenuation data for left channel ADC gain in 0.5dB steps
R14 (0Eh)
0001110
7:0
8
LAG[7:0]
ZCLA
11001111
(0dB)
Attenuation
ADCL
0
Left channel ADC zero cross enable:
0: Zero cross disabled
1: Zero cross enabled
R15 (0Fh)
0001111
7:0
8
RAG[7:0]
ZCRA
11001111
(0dB)
Attenuation data for right channel ADC gain in 0.5dB steps
Attenuation
ADCR
0
Right channel ADC zero cross enable:
0: Zero cross disabled
1: Zero cross enabled
R16 (10h)
0010000
3:0
LCT[3:0]
1011
Limiter Threshold/ALC target level in 1dB steps.
(-5dB)
0000: -16dB FS
0001: -15dB FS
…
ALC Control 1
1101: -3dB FS
1110: -2dB FS
1111: -1dB FS
6:4
MAXGAIN[2:0]
111 (+24dB) Set Maximum Gain of PGA
111 : +24dB
110 : +20dB
….(-4dB steps)
010 : +4dB
001 : 0dB
000 : 0dB
8:7
3:0
LCSEL[1:0]
HLD[3:0]
00
ALC/Limiter function select
00 = Limiter
01 = ALC Right channel only
10 = ALC Left channel only
11 = ALC Stereo (PGA registers unused)
R17 (11h)
0010001
0000
ALC hold time before gain is increased.
0000: 0ms
(0ms)
ALC Control 2
0001: 2.67ms
0010: 5.33ms
… (time doubles with every step)
1111: 43.691s
7
8
ALCZC
LCEN
0 (zero
cross off)
ALC uses zero cross detection circuit.
0
Enable Gain control circuit.
0 = Disable
1 = Enable
R18 (12h)
0010010
3:0
ATK[3:0]
0010
ALC/Limiter attack (gain ramp-down) time
(24ms)
ALC mode
Limiter Mode
ALC Control 3
0000: 8.4ms
0000: 250us
0001: 16.8ms
0001: 500us…
0010: 33.6ms…
(time doubles with every step)
1010 or higher: 8.6s
0010: 1ms
(time doubles with every step)
1010 or higher: 256ms
7:4
DCY[3:0]
0011
(268ms/
9.6ms)
ALC/Limiter decay (gain ramp up) time
ALC mode
Limiter mode
0000: 33.5ms
0001: 67.2ms
0000: 1.2ms
0001: 2.4ms
0010: 134.4ms ….(time
doubles for every step)
0010: 4.8ms ….(time doubles
for every step)
1010 or higher: 34.3ms
1010 or higher: 1.2288s
PP Rev 1.8, June 2004
w
30
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
