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WM8775
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
0000111
3
TOD
0
ADC Analogue PGA Zero cross detect timeout disable
0 : Timeout enabled
Timeout Clock
Disable
1: Timeout disabled
R11 (0Bh)
0001011
1:0
2
ADCFMT[1:0]
ADCLRP
10
0
Interface format select
00: right justified mode
01: left justified mode
10: I2S mode
Interface
Control
11: DSP mode
ADCLRC Polarity or DSP Early/Late mode select
In left/right/ I2S modes:
ADCLRC Polarity (normal)
0 : normal ADCLRC polarity
1: inverted ADCLRC polarity
BITCLK Polarity
DSP Mode
0: Early DSP mode
1: Late DSP mode
3
ADCBCP
0
0: Normal - ADCLRC sampled on rising edge of BCLK;
DOUT changes on falling edge of BCLK.
1: Inverted - ADCLRC sampled on falling edge of BCLK;
DOUT changes on rising edge of BCLK.
5:4
ADCWL[1:0]
10
Input Word Length
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
6
8
ADCMCLK
ADCHPD
0
0
ADCMCLK Polarity
0 : non-inverted
1: inverted
ADC High pass Filter Disable:
0: High pass Filter enabled
1: High pass Filter disabled
Master Mode MCLK:ADCLRC ratio select:
010: 256fs
12 (0Ch)
0001100
2:0
ADCRATE[2:0]
010
Master Mode
Control
011: 384fs
100: 512fs
101: 768fs
3
8
ADCOSR
ADCMS
0
0
ADC oversample rate select
0: 128x oversampling
1: 64x oversampling
Maser/Slave interface mode select
0: Slave Mode – ADCLRC and BCLK are inputs
1: Master Mode – ADCLRC and BCLK are outputs
R13 (0Dh)
0001101
0
1
6
PWDN
ADCPD
AINPD
0
0
0
Chip Powerdown Control (works together with ADCD):
0: All circuits running, outputs are active
Powerdown
Control
1: All circuits in power save mode, outputs muted
ADC powerdown:
0: ADC enabled
1: ADC disabled
Input mux and buffer powerdown
0: Input mux and buffer enabled
1: Input mux and buffer powered down
PP Rev 1.8, June 2004
29
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
