WM8772
Production Data
PIN DESCRIPTION – 32 LEAD TQFP
PIN
1
NAME
ADCLRC
DACLRC
DVDD
DGND
DIN1
TYPE
DESCRIPTION
Digital Input/Output ADC left/right word clock
Digital Input/Output DAC left/right word clock
2
3
Supply
Supply
Digital positive supply
Digital negative supply
DAC channel 1 data input
DAC channel 2 data input
DAC channel 3 data input
ADC data output
4
5
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
6
DIN2
7
DIN3
8
DOUT
ML/I2S
9
Software Mode: Serial interface Latch signal
Hardware Mode: Input Audio Data Format
Software Mode: Serial control interface clock
Hardware Mode: Audio data input word length
Software Mode: Serial interface data
10
11
MC/IWL
MD/DM
Digital Input
Digital Input
Hardware Mode: De-emphasis selection
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MUTE
REFADC
ADCVREFN
DACVREFN
DACVREFP
VMID
Digital Input/Output DAC Zero Flag output or DAC Mute Input
Analogue Output
Supply
ADC reference buffer decoupling pin; 10uF external decoupling
ADC negative supply
Supply
DAC negative supply
Supply
DAC positive reference supply
Midrail divider decoupling pin; 10uF external decoupling
ADC right input
Analogue Output
Analogue Input
Analogue Input
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
AINR
AINL
ADC left input
VOUT1L
VOUT1R
VOUT2L
VOUT2R
VOUT3L
VOUT3R
AGND
DAC channel 1 left output
DAC channel 1 right output
DAC channel 2 left output
DAC channel 2 right output
DAC channel 3 left output
DAC channel 3 right output
Analogue negative supply and substrate connection
Analogue positive supply
Control format selection
AVDD
Supply
MODE
Digital Input
0 = Software control
1 = Hardware control
29
30
31
32
ADCMCLK
DACMCLK
ADCBCLK
DACBCLK
Digital Input
Digital Input
Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency)
Master DAC clock; 256, 384, 512 or 768fs (fs = word clock frequency)
Digital Input/Output ADC audio interface bit clock
Digital Input/Output DAC audio interface bit clock
Note: Digital input pins have Schmitt trigger input buffers.
PD Rev 4.2 October 2005
8
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