Production Data
WM8772
PIN DESCRIPTION – 28 LEAD SSOP
PIN
NAME
TYPE
DESCRIPTION
1
MODE
Digital input
Control format selection
0 = Software control
1 = Hardware control
2
MCLK
Digital input
Master clock; 256, 384, 512 or 768fs (fs = word clock frequency)
(combined ADCMCLK and DACMCLK)
3
4
BCLK
LRC
Digital input/output Audio interface bit clock (combined ADCBCLK and DACBCLK)
Digital input/output Audio left/right word clock (combined ADCLRC and DACLRC)
5
DVDD
DGND
DIN1
Supply
Supply
Digital positive supply
6
Digital negative supply
7
Digital input
Digital input
Digital input
Digital output
Digital input
DAC channel 1 data input
8
DIN2
DAC channel 2 data input
9
DIN3
DAC channel 3 data input
10
11
DOUT
ML/I2S
ADC data output
Software Mode: Serial interface Latch signal
Hardware Mode: Input Audio Data Format
Software Mode: Serial control interface clock
Hardware Mode: Audio data input word length
Software Mode: Serial interface data
Hardware Mode: De-emphasis selection
12
13
MC/IWL
MD/DM
Digital input
Digital input
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MUTE
REFADC
VREFN
VREFP
VMID
Digital input/output DAC Zero Flag output or DAC mute input
Analogue output
Supply
ADC reference buffer decoupling pin; 10uF external decoupling
ADC and DAC negative supply
DAC positive reference supply
Midrail divider decoupling pin; 10uF external decoupling
ADC right input
Supply
Analogue output
Analogue input
Analogue input
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
Supply
AINR
AINL
ADC left input
VOUT1L
VOUT1R
VOUT2L
VOUT2R
VOUT3L
VOUT3R
AGND
DAC channel 1 left output
DAC channel 1 right output
DAC channel 2 left output
DAC channel 2 right output
DAC channel 3 left output
DAC channel 3 right output
Analogue negative supply and substrate connection
Analogue positive supply
AVDD
Supply
Note: Digital input pins have Schmitt trigger input buffers.
PD Rev 4.2 October 2005
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