Production Data
WM8772EDS – 28 LEAD SSOP
1 BCLK
1 BCLK
1/fs
ADCLRC
ADCBCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 29 DSP Mode Audio Interface - Mode A Master, ADC
DSP MODE B
In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the first
BCLK rising edge following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data
follow DAC channel 1 left data (Figure 30).
Figure 30 DSP Mode Audio Interface - Mode B Slave, DAC
1/fs
DACLRC
DACBCLK
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
CHANNEL 3
RIGHT
NO VALID DATA
DIN1
1
2
n
1
2
n
1
2
n
1
n-1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 31 DSP Mode Audio Interface - Mode B Master, DAC
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
BCLK as the low to high LRC transition and may be sampled on the rising edge of BCLK. The right
channel ADC data is contiguous with the left channel data (Figure 32).
PD Rev 4.2 October 2005
27
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
