WM8753L
Advanced Information
RXN and RXP are inputs to a mixer controlled by the RXMSEL register bits. By default this is a
differential input (RXP-RXN). The RX mixer can also be configured as a stereo to mono mix input
(RXP+RXN). Alternatively RXP or RXN can be individually selected as mono inputs with the other
input disabled. The RX mixer has -6dB of gain so that a 0dB signal on RXP and RXN will sum to give
a 0dB signal at the mixer output.
In addition there is a Sidetone path from the Mic Mux to the left, right and mono mixers. This Sidetone
path may be selected to be the output from the left or right ADC input PGA, the Mic1 preamp or the
Mic2 preamp under the control of MICMUX[1:0].
The Left ADC input is selected using LADCSEL[1:0]. It can be selected to be i) a direct analogue
input from LINE1 or the output of the RX mixer block; ii) through the input PGA and ALC mixer; iii) DC
measurement input from LINE1. For direct analogue input the input may be selected from either
LINE1 or the RX mixer using LM. The ALC mixer may be used to mix MIC1, MIC2, LINE and RX
differential inputs, selected using MIC1ALC, MIC2ALC, LINEALC and RXALC.
The Right ADC input is selected using RADCSEL[1:0]. It can be selected to be i) a direct analogue
input from LINE2 or the RX mixer input; ii) through the input PGA from the MIC2 preamp; iii) Record
mixer output. For direct analogue input the input may be selected from either LINE2 or the RX mixer
using RM. The Record mixer may be used to mix the output from the left, right and mono output
mixers, e.g. for recording a phone call. The inputs to the Record mixer are selected using LSEL,
RSEL and MSEL and have independent input gain control from -15dB to +6dB.
The input to the Left ADC PGA via the external dc blocking capacitor is from the output of the ALC
mixer, which allows the mixing of the output from the Line mixer, the RX mixer, the Mic1 preamp and
the Mic2 preamp under the control of LINEALC, RXALC, MIC1ALC and MIC2ALC.
The signal inputs are biased internally to the reference voltage VREF. Whenever the analogue inputs
are muted or the device placed into standby mode, the inputs are kept biased to VREF using special
anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when changing
inputs.
DC MEASUREMENT
For DC measurements (for example, battery voltage monitoring), the input signal at the LINE1 input
can be taken directly into the left ADC, bypassing the PGA. The ADC output then becomes unsigned
relative to AVDD, instead of being a signed (two’s complement) number relative to VREF. The input
range for dc measurement is AGND to AVDD. The ADC high pass filter should be disabled when
measuring DC voltages.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
00
DESCRIPTION
Right ADC Input Select
R46 (2Eh)
RADCSEL[1:0]
[3:2]
ADC input Mode
00 : PGA
01 : LINE2 or RXP-RXN
10 : Left + Right + Mono output Mix
11 : unused
LADCSEL[1:0]
00
Left ADC Input Select
00 : PGA
[1:0]
01 : LINE1 or RXP-RXN
10 : LINE1 DC measurement
11 : unused
Table 3 ADC Input Control
AI Rev 3.1 June 2004
21
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
