WM8753L
Advanced Information
OUTPUT MIXERS
Flexible mixing is provided on the outputs of the device; a stereo mixer is provided for the stereo
headphone or line outputs, and an additional mono mixer for the mono output to the transmit side of
the equipment. Gain adjustment capability, and signal switching is provided to allow for all possible
signal combinations; eg. Sidetone, transmission of stereo music playback along with voice, whilst at
the same time as listening to music, and received phone call if so desired. The output buffers can be
configured in several ways, allowing support of up to three sets of external transducers; ie stereo
headphone, BTL speaker, and BTL earpiece may be connected simultaneously. (thermal implications
should be considered before simultaneous full power operation of all outputs is attempted!)
Alternatively, if a speaker output is not required, the LOUT2 and ROUT2 pins might be used as a
stereo speaker or headphone driver, (disable output invert buffer on ROUT2). In that case either two
sets of headphones might be driven, or the LOUT2 and ROUT2 pins used as a line output driver.
The Earpiece may be driven in BTL mode, with the ROUT1 signal inverted into the OUT3 pin, or
alternatively OUT3 may be either the mono version of ROUT1 and LOUT1, or simply a buffered
version of the chip midrail reference voltage. This voltage may then be used as a headphone ‘pseudo
ground’ allowing removal of the large AC coupling capacitors often used in the output path.
AUDIO INTERFACES
The WM8753L has a pair of audio interfaces, to support the Hi-Fi DAC and the PCM codec.
The Hi-Fi DAC is supported with a 4 wire standard audio DAC interface which supports a number of
audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed
words are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in
master or slave modes.
The PCM codec is connected via standard PCM type interface, comprising a frame sync, FS, a bitclk
VXCLK, (typically 16 clocks per frame), and a pair of data lines for DAC input and ADC output data. A
master clock for the PCM codec (typically 256fs or 2.048MHz when running at 8ks/s) may also be
supplied as an input, if the system controller can provide this, to PCMCLK input pin. In the event of
the system controller not being able to provide this clock, it may be generated in the WM8753L using
PLL2. Note that the MCLK input to the chip must be present for PLL2 to operate, as it is a digital PLL
type of circuit and uses this high speed master clock.
In the event of the PCM codec not being required, (temporarily or otherwise) the ADC output data
may be sent over the hi-fi audio interface using the ADCDAT line. In this case the ADC may be
configured to run at the same sample rate as the hi-fi DAC and use the same clock signals (BCLK
and LRC). It may also be configured to run at a different sample rate and instead use the FS and
VXCLK as the ADC data frame sync and clock. Both interfaces may be configured to run in Master
mode when LRC, BCLK, FS and VXCLK are outputs from the WM8753L. A mixed Master-Slave
mode is also supported allowing BCLK / VXCLK to be outputs from the WM8753L and LRC / FS to be
inputs.
CONTROL INTERFACES
To allow full software control over all its features, the WM8753L offers a choice of 2 or 3 wire MPU
control interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs.
Selection between the modes is via the MODE/GPIO3 pin. In 2 wire mode only slave operation is
supported and the address of the device may be selected between two values using the CSB/GPIO5
pin. The interface mode and 2-wire address select are set on power-up by the sampling of the
MODE/GPIO3 and CSB/GPIO5 pins by the power-on reset. This allows these pins to be used as
GPIO pins after powerup.
CLOCKING SCHEMES
WM8753L offers the normal audio DAC clocking scheme operation, where 256 or 384fs or higher
MCLK is provided to the DAC. Similarly the PCM codec can be operated in normal PCM type mode
where a 256fs clock is sent along with the PCM frame clock and data.
However, a pair of PLLs are also included which may be used to generate these clocks in the event
that they are not available from the system controller. The first PLL1 uses an input clock, typically the
Rf reference clock used in most mobile systems, to generate high quality audio clocks. The second
PLL2 can use this same reference clock. If these PLLs are not required for generation of these
clocks, they can be reconfigured to generate alternative clocks which may then be output and used
elsewhere in the system. The WM8753L can also generate standard audio clock rates from a 12 or
24MHz USB clock without the use of the PLLs.
AI Rev 3.1 June 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
