WM8750-EV1M
GND
ADCDAT
H2
Figure 26 Data Connection to the DSP Platform (+5V tolerant input levels)
When the WM8750 is set to Master Mode, the jumpers on header H1 should be removed,
disconnecting the digital input section of the evaluation board. If an external MCLK signal is
being used (i.e. supplied by the DSP) then the DSP platform should be connected as shown
in Figure 27. The signal should be connected to H1 and not to the header strip J15 running
up the side of the device. Connecting the signal to the output side of the level-shift IC (U4)
will cause drive contention between U4 and the DSP and could result in damage to either or
both devices. In most cases, the DSP supplies will be set around +3V for low power portable
applications. The inputs to the level-shift IC (74ALVC164245) have a TTL threshold (i.e.
Logic High = +2V(min); Logic Low = +0.8V(max)) and low input current requirements (i.e.
15uA max) allowing most DSPs to connect directly.
MCLK
GND
H1
Figure 27 Timing Connections from DSP Platform
The digital inputs to the WM8750 have a CMOS threshold (i.e. Logic High (min) =
DBVDDx0.7; Logic Low (max) = DBVDDx0.3). These are met directly by the level shift IC
outputs.
The jumpers on H2 should also be removed, disconnecting the digital output section of the
WM8750 evaluation board. The ADCDAT, BCLK and ADCLRC signals from the WM8750
should then be connected to the DSP from headers J15 and J21 running up each side of the
WM8750.
The ADCDAT, BCLK and ADCLRC signals should be taken direct from the WM8750 digital
output as the output side of the level-shift IC (U4) from the WM8750 is pulled up to +5V
which may overdrive and cause damage to the DSP inputs. The digital output levels of the
WM8750 are Logic High (min) = DBVDDx0.9; Logic Low (max) = DBVDDx0.1 which should
meet the input level requirements of most DSPs running at +3V supplies. If the DSP is
running with +5V supplies (and +5V tolerant inputs) then the connections from the WM8750
evaluation board to the DSP should be made from H2 on the output side of the level-shift IC
from the WM8750 as shown in Figure 28.
GND
ADCDAT
GND
ADCLRC
GND
BCLK
H2
Figure 28 Connections to the DSP Platform (+5V tolerant input levels)
This will ensure that the DSP input level specifications are met.
Rev 2.0, February 2005
39
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
