WM8746
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Left and Right DACs soft mute control
0000010
0
MUTE
0
DAC Control
0: No Mute
1: Mute
1
2
DEEMPH
PWDN
ATC
0
0
De-emphasis Control
0: Normal Response (see Figure 14 - Figure 17)
1: De-emphasis Response (see Figure 18 - Figure 23)
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
Attenuator Control
0
3
4
0: All DACs use attenuations as programmed.
1: Right chan. DACs use corresponding left DAC attenuations
Infinite zero detection circuit control and automute control
0: Infinite zero detect disabled
IZD
0
1: Infinite zero detect enabled
8:5
PL[3:0]
1001
DAC Output Control
PL[3:0]
Left
Right
PL[3:0]
Left
Right
Output
Output
Output
Output
0000
0001
0010
0011
0100
0101
0110
0111
Mute
Left
Mute
Mute
Mute
Mute
Left
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Right
Right
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Mute
Left
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Left
Right
(L+R)/2
Left
Right
(L+R)/2
Left
0000011
1:0
FMT[1:0]
LRP
00
0
Interface format select
00: right justified mode
Interface
Control
01: left justified mode
10: I2S mode
11: DSP Mode A or B
2
LRCIN Polarity or LRCIN Phase
Left Justified / Right Justified / I2S
0: Standard LRCIN Polarity
1: Inverted LRCIN Polarity
BCKIN Polarity
DSP Mode
0: DSP Mode A
1: DSP Mode B
3
BCP
0
0: Normal (DIN[2:0] and LRCIN sampled on rising edge)
1: Inverted (DIN[2:0] and LRCIN sampled on falling edge)
5:4
WL[1:0]
10
Input Word Length
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
Controls the output phase of the three stereo channels
Bit 6 reverses the phase of data output on OUT0L/R.
Bit 7 reverses the phase of data output on OUT1L/R.
Bit 8 reverses the phase of data output on OUT2L/R.
8:6
PHASE
000
March 2006, PD Rev 4.0
24
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
