WM8746
Production Data
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description.
There are 9 registers with 9 bits per register. These can be controlled using the Control Interface.
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
D8
D7
L0A7
R0A7
PL2
D6
L0A 6
R0A 6
PL1
D5
L0A 5
R0A 5
PL0
D4
L0A 4
R0A 4
IZD
D3
L0A 3
R0A 3
ATC
D2
L0A 2
R0A 2
D1
L0A 1
R0A 1
D0
L0A 0
R0A 0
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
UPDATE
UPDATE
PL3
0
0
0
0
0
0
1
0
0
0
0
0
1
0
PDWN DEEMPH MUTE
0
0
0
0
0
1
1
REV2
REV1
L1A7
R1A7
L2A7
R2A7
REV0
L1A 6
R1A 6
L2A 6
R2A 6
IWL1
L1A 5
R1A 5
L2A 5
R2A 5
IWL0
L1A 4
R1A 4
L2A 4
R2A 4
BCP
LRP
FMT1
L1A 1
R1A 1
L2A 1
R2A 1
FMT0
L1A 0
R1A 0
L2A 0
R2A 0
0
0
0
0
1
0
0
UPDATE
UPDATE
UPDATE
UPDATE
L1A 3
R1A 3
L2A 3
R2A 3
L1A 2
R1A 2
L2A 2
R2A 2
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
UPDATE MASTA7 MASTA 6 MASTA 5 MASTA 4 MASTA 3 MASTA 2 MASTA 1 MASTA 0
ZCD 2SPD
0
0
0
1
0
0
1
0
0
0
0
0
0
0
Table 12 Register Map
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000000
7:0
L0A[7:0]
11111111
(0dB)
Attenuation level of left channel DACL0 in 0.5dB steps, see Table 8.
Attenuation
DACL0
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store DACL0 in intermediate latch (no change to output)
1: Store DACL0 and update attenuation on all channels.
0000001
7:0
8
R0A[7:0]
UPDATE
11111111
(0dB)
Attenuation level of left channel DACR0 in 0.5dB steps, see Table 8.
Attenuation
DACR0
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store DACR0 in intermediate latch (no change to output)
1: Store DACR0 and update attenuation on all channels.
March 2006, PD Rev 4.0
23
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
