WM8746
Production Data
POWERDOWN MODE
Setting the PWDN register bit immediately connects all outputs to VCAP and selects a low power
mode. All trace of the previous input samples is removed, but all control register settings are
preserved. When PWDN is cleared again the first 16 input samples will be ignored as the FIR will
repeat it's power-on initialisation sequence.
REGISTER ADDRESS
0000010
BIT
LABEL
DEFAULT
DESCRIPTION
Power Down Mode Select:
0 : Normal Mode
2
PWDN
0
DAC Channel Control
1: Power Down Mode
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channels for all three pairs of DACs from the next audio input sample. No update to the
attenuation registers is required for ATC to take effect.
REGISTER ADDRESS
0000010
BIT
LABEL
DEFAULT
DESCRIPTION
3
ATC
0
Attenuator Control Mode:
DAC Channel Control
0 : Right channels use Right
attenuations
1: Right Channels use Left
Attenuations
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS
0000010
BIT
LABEL
DEFAULT
DESCRIPTION
8:5
PL[3:0]
1001
PL[3:0]
Left
Right
Output
Output
DAC Control
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Mute
Mute
Mute
Mute
Left
Right
(L+R)/2
Mute
Left
Left
Right
(L+R)/2
Mute
Left
Left
Left
Right
Right
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Table 6 Input to Output Control
March 2006, PD Rev 4.0
18
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
