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WM8728SEDS 参数 Datasheet PDF下载

WM8728SEDS图片预览
型号: WM8728SEDS
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz的立体声DAC,具有音量控制 [24-bit, 192kHz Stereo DAC with Volume Control]
分类和应用: 转换器光电二极管
文件页数/大小: 28 页 / 345 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8728  
Production Data  
DE-EMPHASIS MODE  
Setting the DEEMPH register bit puts the digital filters into de-emphasis mode:  
REGISTER ADDRESS  
0010  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
1
DEEMPH  
0
De-emphasis mode select:  
0 : De-emphasis Off  
DAC Control  
1: De-emphasis On  
Table 12 De-emphasis Control  
POWERDOWN MODE  
Setting the PWDN register bit immediately connects all outputs to VMID and selects a low power  
mode. All trace of the previous input samples is removed, and all control register settings are  
cleared. When PWDN is cleared again the first 16 input samples will be ignored, as the FIR will  
repeat it's power-on initialisation sequence.  
REGISTER ADDRESS  
0010  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Power Down Mode Select:  
0 : Normal Mode  
2
PWDN  
0
DAC Control  
1: Power Down Mode  
Table 13 Powerdown control  
DIGITAL AUDIO INTERFACE CONTROL REGISTERS  
The WM8728 has a fully featured digital audio interface that is a superset of that contained in the  
WM8716. Interface format is selected via the IWL[2:0] register bits in register M2 and the I2S  
register bit in M3.  
REGISTER ADDRESS  
0010  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
5:3  
IWL[2:0]  
000000  
Interface format Select  
DAC Control  
0011  
0
I2S  
0
Interface format Select  
Interface Control  
Table 14 Interface Format Controls  
IW2  
I2S  
IW1  
IW0  
AUDIO INTERFACE DESCRIPTION  
(NOTE 1)  
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
16 bit right justified mode  
20 bit right justified mode  
24 bit right justified mode  
24 bit left justified mode  
16 bit I2S mode  
24 bit I2S mode  
20 bit I2S mode  
20 bit left justified mode  
16 bit DSP mode  
20 bit DSP mode  
24 bit DSP mode  
32 bit DSP mode  
16 bit left justified mode  
Table 15 Audio Data Input Format  
Note:  
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the  
DAC is programmed to receive 16 or 20 bit data, the WM8728 pads the unused LSBs with  
ZEROS. If the DAC is programmed into 32-bit mode, the 8 LSBs are treated as zero.  
PD Rev 4.2 April 2004  
21  
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