WM8725
Production Data
PIN DESCRIPTION
PIN
1
NAME
LRCIN
TYPE
Digital input
DESCRIPTION
Sample rate clock input
Serial data input
DIN
Digital input
Digital input
No connect
Analogue output
Analogue output
Supply
2
BCKIN
NC
Bit clock input
3
No internal connection
4
CAP
Analogue internal reference
Right channel DAC output
0V supply
5
VOUTR
GND
6
7
VDD
Supply
Positive supply
8
VOUTL
MUTE
NC
Analogue output
Digital input
No connect
Digital input
Digital input
Digital input
Left channel DAC output
Mute control, high = muted. Internal pull-down
No internal connection
9
10
11
12
13
14
DEEMPH
FORMAT
SCKI
De-emphasis select, high = de-emphasis ON. Internal pull-up
Data input format select, low = normal, high = I2S. Internal pull-up
System clock input (256fs or 384fs)
INTERNAL POWER ON RESET
The WM8725 includes an internal power-on reset circuit. This is shown in Figure 1.This reset
circuit is used to reset the digital logic into a default state after power up.
Figure 1 Internal Power on Reset Circuit
The timing of the power on reset is shown in Figure 2 The circuit monitors VDD and VMID
(CAP pin) and asserts PORB low when VMID is below the minimum threshold Vpor. It is
assumed that VMID will rise slower than VCC due to the capacitor on VMID.
PD, Rev 4.3, February 2012
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
