WM8711BL
Production Data
REGISTER MAP
The complete register map is shown in Table 23. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
B
B
B
B
B
B
B
9
B8
B7
B6
B5
B4
B3
B2
B1
B0
15 14 13 12 11 10
LRHP
BOTH
RLHP
BOTH
0
R2 (04h)
R3 (06h)
0
0
0
0
0
0
0
0
0
0
1
1
0
1
LZCEN
RZCEN
LHPVOL
RHPVOL
R4 (08h)
R5 (0Ah)
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
DAC SEL BYPASS
DAC MU
0
0
1
0
0
0
0
DEEMPH
POWER
OFF
BCLK
INV
CLK
OUTPD
R6 (0Ch)
R7 (0Eh)
R8 (10h)
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
0
0
OSCPD OUTPD DACPD
1
1
MS
LR SWAP LRP
IWL
FORMAT
CLK0
DIV2
0
CLKI
DIV2
0
USB/
NORM
0
0
SR
BOSR
0
R9 (12h)
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
ACTIVE
R15(1Eh)
RESET
ADDRESS
Table 22 Mapping of Program Registers
DATA
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000010
6:0
LHPVOL
[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
Left Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
Left Channel Zero Cross detect Enable
1 = Enable
7
8
LZCEN
0
0
0 = Disable
LRHPBOTH
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
PD, Rev 4.2, December 2011
3444
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
