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WM8591
ADCBCLK and DACBCLK are also generated by the WM8591. The frequency of ADCBCLK and
DACBCLK can be set in software.
BCLK can be set to MCLK/4, 64fs or 128fs. If DSP mode is selected as the audio interface mode
then BCLK can be set to MCLK, 64fs or 128fs. Note that DSP mode cannot be used in 128fs mode
for word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits.
REGISTER ADDRESS
R28 (1Ch)
BIT
LABEL
DEFAULT
DESCRIPTION
3:2
BCLK_RATE
00
Sets ADCBCLK and DACBCLK rate in master mode
0011100
BCLK_RATE
BCLK Output Frequency
MCLK/4 (MCLK in DSP Mode)
MCLK/4 (MCLK in DSP Mode)
64fs
ADC/DAC Synchronization
00
01
10
11
128fs
ZERO DETECT
The WM8591 has a zero detect circuit for each DAC channel, which detects when 1024 consecutive
zero samples have been input. The two zero flag outputs (ZFLAGL and ZFLAGR) may be
programmed to output the zero detect signals (see Table 9) that may then be used to control external
muting circuits. The ZFLAGL and ZFLAGR pins require a pull-up resistor to be connected (see
external components diagram). The ZFLAGL and ZFLAGR pads will pull low to indicate that the zero
condition has been detected.
The polarity of the zero flag signals can be changed by setting the ZFLAGPOL bit. When this bit is
set, the ZFLAGL and ZFLAGR pins will pull low when the zero condition is not found and will go to
high impedance when the zero condition is detected.
The zero detect may also be used to automatically enable the mute by setting IZD. The zero flag
output may be disabled by setting DZFM to 00.
REGISTER ADDRESS
R9 (09h)
BIT
LABEL
DEFAULT
DESCRIPTION
2:1
DZFM
10
ZFLAG decode
0001001
DZFM
ZFLAGL
ZFLAGR
DAC Mute
00
01
10
11
Zero flag disabled
Left channel zero
Both channel zero
Either channels zero
Zero flag disabled
Right channel zero
Both channel zero
Either channel zero
4
ZFLAGPOL
0
ZFLAG polarity
ZFLAGPOL
ZFLAGL
ZFLAGR
Pin pulls low to indicate zero conidition,
high impedance otherwise
0
1
Pin is high impedance when zero
condition detected, pulls low otherwise
Table 9 Zero Flag Control
POWERDOWN MODES
The WM8591 has powerdown control bits allowing specific parts of the WM8591 to be powered off
when not being used. Control bit ADCPD powers off the ADC. The stereo DAC has a separate
powerdown control bit, DACPD allowing the DAC to be powered off when not in use.
Setting ADCPD and DACPD will powerdown everything except the references VMID, REFN and
REFP. Setting PDWN will override all other powerdown control bits. It is recommended that ADCPD
and DACPD are set before setting PDWN. The default is for all blocks to be enabled.
PP Rev 1.0 May 2005
15
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
