Product Preview
WM8591
DEVICE DESCRIPTION
INTRODUCTION
WM8591 is a complete differential 2-channel DAC, single-ended 2-channel ADC audio CODEC,
including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched
capacitor multi-bit sigma delta DACs with output smoothing filters. It is available in a single package
and controlled by a 2-wire serial interface.
The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/Os. The
Audio Interfaces may be independently configured to operate in either master or slave mode. In
Slave mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In Master mode ADCLRC,
DACLRC, ADCBCLK and DACBCLK are outputs.
The ADC has an analogue input PGA and a digital gain control, accessed by one register write. The
input PGA allows input signals to be gained up to +24dB and attenuated down to -21dB in 0.5dB
steps. The digital gain control allows attenuation from -21.5dB to -103dB in 0.5dB steps. This allows
the user maximum flexibility in the use of the ADC.
The DAC has its own digital volume control, which is adjustable between 0dB and -127.5dB in 0.5dB
steps. In addition a zero cross detect circuit is provided for digital volume controls. The digital
volume control detects a transition through the zero point before updating the volume. This
minimises audible clicks and ‘zipper’ noise as the gain values change.
Control of internal functionality of the device is by 2-wire serial control interface. The interface may be
asynchronous to the audio data interface as control data will be re-synchronised to the audio
processing internally.
Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs (DAC only) is
provided. ADC and DAC may run at different rates. Master clock sample rates (fs) from less than
32kHz up to 192kHz are allowed, provided the appropriate system clock is input.
The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP
serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The WM8591 uses separate master clocks for the ADC and DAC. The external master
system clocks can be applied directly through the ADCMCLK and DACMCLK input pins with no
software configuration necessary. In a system where there are a number of possible sources for the
reference clock it is recommended that the clock source with the lowest jitter be used to optimise the
performance of the ADC and DAC.
In Slave mode the WM8591 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output
level at the last sample. The master clock must be synchronised with ADCLRC/DACLRC, although
the WM8591 is tolerant of phase variations or jitter on this clock.
The ADC supports system clock to sampling clock ratios of 256fs to 768fs. The DACs support ratios
of 256fs to 1152fs when the DAC signal processing of the WM8591 is programmed to operate at 128
times oversampling rate (DACOSR=0). The DACs support system clock to sampling clock ratios of
128fs and 192fs when the WM8591 is programmed to operate at 64 times oversampling rate
(DACOSR=1).
The ADC signal processing in the WM8591 can operate at either 128 times oversampling rate
(ADCOSR=0) or 64 times oversampling rate (ADCOSR=1). It is recommended that ADCOSR is set
to 1 for ADC operation at 96kHz.
PP Rev 1.0 May 2005
13
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
