WM8591
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ADCBCLK/
DACBCLK
(Output)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
DOUT
DIN
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADC/DACLRC propagation
delay from ADC/DACBCLK
falling edge
tDL
0
10
ns
DOUT propagation delay
from ADCBCLK falling edge
tDDA
tDST
tDHT
0
10
ns
ns
ns
DIN setup time to
DACBCLK rising edge
10
10
DIN hold time from
DACBCLK rising edge
Table 2 Digital Audio Data Timing – Master Mode
DIGITAL AUDIO INTERFACE – SLAVE MODE
DACBCLK
ADCBCLK
ADCLRC
DVD
Controller
WM8591
CODEC
DACLRC
DOUT
DIN
Figure 4 Audio Interface – Slave Mode
PP Rev 1.0 May 2005
10
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
