Production Data
WM8580
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8
CLKSEL
08h
5:4
TX_CLKSEL
01
S/PDIF Transmitter clock source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
Table 35 S/PDIF Transmitter Clock Control
PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX)
The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied
externally (slave mode) or they can be generated internally by the WM8580 (master mode). The
master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this
module is described on page 22. The clock supplied to this module is selected by the
PAIFRXMS_CLKSEL register bits and can be MCLK, PLLACLK, or PLLBCLK.
Figure 29 PAIF Receiver Clock Selection
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R9
PAIF 1
09h
7:6
PAIFRXMS_
CLKSEL
00
PAIF Receiver Master Mode clock
source
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
Table 36 PAIF Receiver Master Mode Clock Control
PD Rev 4.3 August 2007
45
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