WM8580
Production Data
CLOCK SELECTION
To accompany the flexible digital routing options, the WM8580 offers a clock configuration scheme
for each interface. By default, the user can choose the interface clock from MCLK, ADCMCLK,
PLLACLK or PLLBCLK, with some restrictions which are autoconfigured. For example, if the S/PDIF
receiver is routed to the DAC, appropriate interface clocks are autoconfigured. These are described
in the following sections.
For some interfaces, the rate can be controlled either by external LRCLK (slave mode), internal
LRCLK (master mode) or by control register. The available options are described below.
It is possible to override the autoconfiguration, allowing the user to manually select any available
clock for any interface using the appropriate CLKSEL register bits.
DAC INTERFACE
The DAC_CLKSEL register selects the DAC clock source from MCLK, PLLACLK or PLLBCLK. If the
digital routing has been set such that DAC1 is sourcing the S/PDIF Receiver, then PLLACLK is
automatically selected, and DACs 2/3 are powered down by default.
A DAC can source data from 3 different places. The rate (OSR) at which the DACs operate is
determined by the DAC Rate module, which divides down the MCLK signal. It calculates the OSR
rate based on the digital routing setup, and selects between 128/192/256/384/512/768/1152fs
If DAC source = PAIFRX, then the PAIFRX_LRCLK is used to calculate the OSR of the DAC.
If DAC source = SAIFRX, then the SAIFRX_LRCLK is used to calculate the OSR of the DAC
If DAC source = SPDIFRX then either the SFRM_CLK (default) or the PAIFRX_LRCLK is used to
calculate the OSR of the DAC. The selection of which clock to use is done using the
RX2DAC_MODE selection bit.
If DAC1 source = S/PDIFRX, and DAC2/DAC3/DAC4 are not used then the rate generator uses the
SFRM_CLK (the sub-frame clock),
If DAC2/3 are used to source the PAIFRX, then to synchronize all DACs together, the DAC rate
generator needs to use a common LRCLK. In this case the PAIFRX_LRCLK should be used This is
done by setting the RX2DAC_MODE register bit, allowing the PAIF_LRCLK to be used to generate
the sampling rate. In this case the S/PDIF sampling rate must be synchronised with PAIF_LRCLK.
Also, when using the S/PDIF receiver, the PLLACLK and PLLBCLK are not available, and the MCLK
applied to the DACs must be at a standard audio rate.
Figure 26 DAC Clock Selection
PD Rev 4.3 August 2007
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
