Production Data
WM8580
Figure 31 SAIF Clock Selection
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11
SAIF 1
0Bh
7:6
SAIFMS_
CLKSEL
11
SAIF Master Mode clock source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
Table 37 SAIF Master Mode Clock Control
MANUAL CLOCK SELECTION
It is possible to override all default clocking configuration restrictions by setting CLKSEL_MAN. When
CLKSEL_MAN is set, default clocking configurations such as automatic selection of PLLACLK for
DAC1 when DACSRC=00 (S/PDIF received data) are not applied. Instead, clock selection is
determined only by the relevant CLK_SEL register.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8
CLKSEL
08h
6
CLKSEL_MAN
0
Clock selection auto-configuration
override
0 = auto-configuration enabled,
clock configuration follows
restrictions described in page 42
to page 47.
1 = auto-configuration disabled,
clock configuration follows
relevant CLKSEL bits in R8 to
R11.
Table 38 Manual Clock Selection
PD Rev 4.3 August 2007
47
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
