Production Data
WM8580
In DSP modes A and B, left and right channels must be time multiplexed and input on the input data
line on the Audio Interface. For the PAIF Receiver, all three left/right DAC channels are multiplexed
on DIN1 (assuming DAC_SEL = 00). LRCLK is used as a frame synchronisation signal to identify the
MSB of the first word. The minimum number of BCLKs per LRCLK period is six times the selected
word length. Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly
positioned.
LEFT JUSTIFIED MODE
In Left Justified mode, the MSB of the input data is sampled by the WM8580 on the first rising edge
of BCLK following a LRCLK transition. The MSB of the output data changes on the same falling edge
of BCLK as LRCLK and may be sampled on the next rising edge of BCLK. LRCLK is high during the
left samples and low during the right samples.
Figure 14 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In Right Justified mode, the LSB of input data is sampled on the rising edge of BCLK preceding a
LRCLK transition. The LSB of the output data changes on the falling edge of BCLK preceding a
LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLKs are high during the
left samples and low during the right samples.
Figure 15 Right Justified Mode Timing Diagram
PD Rev 4.3 August 2007
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