WM8580
Production Data
•
PLL User Mode (Selected if S/PDIF Receiver Disabled)
In user mode, the user has full control over the function and operation of both PLLA and PLLB. In
this mode, the user can accurately specify the PLL N and K multiplier values and the pre and post-
scale divider values and can hence fully control the generated clock frequencies.
Refer to Table 41 and Table 43 for details of the registers available for configuration in this mode.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R0
PLLA 1/
DEVID1
00h
8:0
PLLA_K[8:0]
100100001
Fractional (K) part of PLLA
frequency ratio (R).
Value K is one 22-digit binary
number spread over registers R0,
R1 and R2 as shown.
R1
8:0
PLLA_K[17:9]
101111110
PLLA 2/
DEVID2
01h
R2
3:0
7:4
PLLA_K[21:18]
PLLA_N[3:0]
1101
0111
PLLA 3/
DEVREV
02h
Integer (N) part of PLLA frequency
ratio (R).
Use values in the range 5 ≤ PLLA_N
≤ 13 as close as possible to 8
R4
PLLB 1
04h
8:0
8:0
PLLB_K[8:0]
PLLB_K[17:9]
100100001
101111110
Fractional (K) part of PLLB
frequency ratio (R).
Value K is one 22-digit binary
number spread over registers R4,
R5 and R6 as shown.
R5
PLLB 2
05h
Note: PLLB_K must be set to
specific values when the S/PDIF
receiver is used. Refer to S/PDIF
Receive Mode Clocking section
for details.
R6
3:0
7:4
PLLB_K[21:18]
PLLB_N[3:0]
1101
0111
PLLB 3
06h
Integer (N) part of PLLB frequency
ratio (R).
Use values in the range 5 ≤ PLLB_N
≤ 13 as close as possible to 8
Note: PLLB_N must be set to
specific values when the S/PDIF
receiver is used. Refer to S/PDIF
Receive Mode Clocking section
for details.
Table 41 User Mode PLL_K and PLL_N Multiplier Control
PLL USER
PARAMETER
PRESCALE_A
PRESCALE_B
PLLA_N
MODE
Manual
Manual
Manual
Manual
Manual
Manual
Manual
Manual
Manual
Manual
PLL S/PDIF RECEIVER MODE
Write PRESCALE_B Value
Configure Specified PLLB Frequency
Automatically Controlled
Automatically Controlled
Configure Specified PLLB Frequency
Configure Specified PLLB Frequency
Automatically Controlled
Not Used
PLLA_K
PLLB_N
PLLB_K
FREQMODE_A
FREQMODE_B
POSTSCALE_A
POSTSCALE_B
256fs/128fs PLLACLK Select
Not Used
Table 42 PLL Control Register Function in PLL User and PLL S/PDIF Receiver Modes
PD Rev 4.3 August 2007
50
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
