Production Data
WM8580
The oscillator XOUT pin has one control bit as shown in Table 39.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R51
PWRDN 2
33h
0
OSCPD
0
Oscillator XOUT Power Down
0 = Power Up XOUT (crystal mode)
1 = Power Down XOUT (CMOS
clock input mode)
Table 39 Oscillator Control
PHASE-LOCKED LOOP (PLL)
The WM8580 has two on-chip phase-locked loop (PLL) circuits which can be used to synthesise two
independent clock signals (PLLACLK and PLLBCLK) from the external oscillator clock. The PLLs can
be used to:
•
Generate clocks necessary for the S/PDIF receiver to lock on to and recover S/PDIF data
from an incoming S/PDIF data stream.
•
•
Generate clocks which may be used to drive the MCLK and/or CLKOUT pins.
Generate clocks which may be used by the S/PDIF transmitter to encode and transmit a
S/PDIF data stream.
•
•
Generate clocks which may be used as the master clock source for the the ADC and
DACs.
Generate clocks which may be used by the master mode clock generator to generate the
BCLK and LRCLK signals for the digital audio interfaces.
The PLLs can be enabled or disabled using the register bits shown in Table 40.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R51
PWRDN 2
33h
1
2
PLLAPD
PLLBPD
1
1
PLL Power Down Control
0 = Power Up PLL
1 = Power Down PLL
Table 40 PLL Power Down Control
The PLLs have two modes of operation:
•
PLL S/PDIF Receive Mode (Selected if S/PDIF Receiver Enabled)
In S/PDIF receive mode, PLLA is automatically controlled by the S/PDIF receiver to allow the
receiver to use PLLA to track and lock on to the incoming S/PDIF data stream. In this case, CLK1 is
automatically maintained at a constant frequency of 256fs relative to the sample rate of the
recovered S/PDIF stream. PLLB must be configured to produce CLK2, a specific reference clock for
the S/PDIF receiver.
PLLACLK may be used as a 256fs or 128fs (selectable – refer to Table 45) master clock source
when in S/PDIF receiver mode. PLLBCLK is not available and must not be selected as the clock
source for any internal function when the S/PDIF receiver is enabled.
If the sample frequency of the incoming stream is changed and PLLA is forced to unlock in order to
track to the new sample frequency, the PLLACLK signal will be stopped until the S/PDIF receiver
has locked to the incoming stream at the new sample frequency. If the incoming S/PDIF stream
stops, the PLLA_ N and PLLA_K values will be frozen and the PLLACLK will continue at the
frequency set by the last recovered S/PDIF stream.
Refer to Table 41 and Table 43 for details of the registers available for configuration in this mode.
Refer to the S/PDIF Receive Mode Clocking section on page 54 for full details.
PD Rev 4.3 August 2007
49
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
