WM8580
Production Data
PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE)
The WM8580 is equipped with two independent phase-locked loop clock generators and a
comprehensive clocking scheme which provides maximum flexibility and function and many
configurable routing possibilities for the user in software mode. An overview of the software mode
clocking scheme is shown in Figure 32.
Figure 32 PLL and Clock Select Circuit
OSCILLATOR
The function of the oscillator is to generate the OSCCLK oscillator clock signal. This signal may be
used as:
•
•
•
The clock source for the PLLs.
A selectable clock source for the MCLK pin, when the pin is configured as an output.
A selectable clock source for the CLKOUT pin, when enabled.
Whenever the PLLs or the S/PDIF receiver is enabled, the OSCCLK signal must be present to
enable the PLLs to generate the necessary clock signals.
The oscillator uses a Pierce type oscillator drive circuit. This circuit requires an external crystal and
appropriate external loading capacitors. The oscillator circuit contains a bias generator within the
WM8580 and hence an external bias resistor is not required. Crystal frequencies between 10 and
14.4MHz or 16.28MHz and 27MHz can be used in software mode. In this case the oscillator XOUT
must be powered up using the OSCPD bit. The recommended circuit is shown in the recommended
components diagram, please refer to Figure 49.
Alternatively, an external CMOS compatible clock signal can be applied to the XIN pin in the absence
of a crystal. This is not recommended when using the PLL as the PLL requires a jitter-free OSCCLK
signal for optimum performance. In this case the oscillator XOUT can be powered down using the
OSCPD bit.
PD Rev 4.3 August 2007
48
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
