Production Data
WM8580
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R9
PAIF 1
09h
5
PAIFRX
MS
0
PAIF Receiver Master/Slave Mode Select:
0 = Slave Mode
1 = Master Mode
R10
5
5
PAIFTX
MS
0
0
PAIF Transmitter Master/Slave Mode Select:
0 = Slave Mode
PAIF 2
0Ah
1 = Master Mode
R11
SAIFMS
SAIF Master/Slave Mode Select:
0 = Slave Mode
SAIF 1
0Bh
1 = Master Mode
Table 12 Master Mode Registers
The frequency of a master mode LRCLK is dependant on system clock and the RATE register
control bits. Table 13 shows the settings for common sample rates and system clock frequencies.
SAMPLING RATE
MCLK CLOCK FREQUENCY (MHZ)
(LRCLK)
128fs
RATE =000
4.096
192fs
RATE =001
6.144
256fs
RATE =010
8.192
384fs
RATE =011
12.288
512fs
RATE =100
16.384
768fs
RATE =101
24.576
1152fs
RATE =110
36.864
32kHz
44.1kHz
48kHz
5.6448
6.144
8.467
11.2896
12.288
16.9344
18.432
22.5792
24.576
33.8688
36.864
Unavailable
Unavailable
9.216
88.2kHz
96kHz
11.2896
12.288
22.5792
24.576
16.9344
18.432
33.8688
36.864
22.5792
24.576
33.8688
36.864
Unavailable Unavailable Unavailable
Unavailable Unavailable Unavailable
176.4kHz
192kHz
Unavailable Unavailable Unavailable Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable Unavailable
Table 13 Master Mode MCLK / LRCLK Frequency Selection
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R9
PAIF 1
09h
2:0
PAIFRX_RATE
[2:0]
010
Master Mode MCLK/LRCLK
Ratio:
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
R10
2:0
2:0
PAIFTX_RATE
[2:0]
010
010
PAIF 2
0Ah
R11
SAIF_RATE
[2:0]
SAIF 1
0Bh
Table 14 Master Mode RATE Registers
In master mode, the BCLKSEL register controls the number of BCLKs per LRCLK. If the
MCLK:LRCLK ratio is 128fs or 192fs and BCLKSEL = 10, BCLKSEL is overwritten to be 128
BCLKs/LRCLK. Also, if BCLKSEL = 00, and LRCLK is 192fs or 1152fs, the generated BCLK has a
mark-space ratio of 1:2.
PD Rev 4.3 August 2007
23
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
