WM8580
Production Data
Figure 8 3-Wire SPI Compatible Control Interface Non-Continuous Readback
2-WIRE SERIAL CONTROL MODE WITH READ-BACK
The WM8580 supports software control via a 2-wire read/write serial bus. Many devices can be
controlled by the same bus, and each device has a unique 7-bit address (see Table 10).
The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK
remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus
respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit,
MSB first). If the device address received matches the address of the WM8580, the WM8580
responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised, the
WM8580 returns to the idle condition and wait for a new start condition and valid address.
Once the WM8580 has acknowledged a correct address, the controller sends the first byte of control
data (REGA(6:0), i.e. the WM8580 register address plus the first bit of register data). The WM8580
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (DIN(7:0),, i.e. the remaining 8 bits of register data), and the
WM8580 acknowledges by driving SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8580 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device returns to the idle condition.
Figure 9 2-Wire Serial Control Interface
The WM8580 has two possible device addresses, which can be selected using the CSB pin.
CSB STATE
DEVICE ADDRESS IN 2-
WIRE MODE
ADDRESS (X=R/W BIT)
X=0 X= 1
0x34
0x36
Low or Unconnected
High
0011010x
0011011x
0x35
0x37
Table 10 2-Wire MPU Interface Address Selection
PD Rev 4.3 August 2007
20
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