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WM8352 参数 Datasheet PDF下载

WM8352图片预览
型号: WM8352
PDF下载: 下载PDF文件 查看货源
内容描述: 欧胜音频Plusa ? ¢立体声CODEC与电源管理 [Wolfson AudioPlus™ Stereo CODEC with Power Management]
分类和应用:
文件页数/大小: 336 页 / 2353 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8352  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Overcurrent interrupt.  
REFER TO  
R29 (1Dh)  
Over Current  
Interrupt  
15  
OC_LS_EINT  
0
(Rising Edge triggered)  
Note: This bit is cleared once read.  
status  
Register 1Dh Over Current Interrupt status  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
R30 (1Eh)  
GPIO  
Interrupt  
Status  
12  
GP12_EINT  
0
GPIO12 interrupt.  
(Trigger controlled by GP12 registers.)  
Note: This bit is cleared once read.  
GPIO11 interrupt.  
11  
10  
9
GP11_EINT  
GP10_EINT  
GP9_EINT  
GP8_EINT  
GP7_EINT  
GP6_EINT  
GP5_EINT  
GP4_EINT  
GP3_EINT  
GP2_EINT  
GP1_EINT  
GP0_EINT  
0
0
0
0
0
0
0
0
0
0
0
0
(Trigger controlled by GP11 registers.)  
Note: This bit is cleared once read.  
GPIO10 interrupt.  
(Trigger controlled by GP10 registers.)  
Note: This bit is cleared once read.  
GPIO9 interrupt.  
(Trigger controlled by GP9 registers.)  
Note: This bit is cleared once read.  
GPIO8 interrupt.  
8
(Trigger controlled by GP8 registers.)  
Note: This bit is cleared once read.  
GPIO7 interrupt.  
7
(Trigger controlled by GP7 registers.)  
Note: This bit is cleared once read.  
GPIO6 interrupt.  
6
(Trigger controlled by GP6 registers.)  
Note: This bit is cleared once read.  
GPIO5 interrupt.  
5
(Trigger controlled by GP5 registers.)  
Note: This bit is cleared once read.  
GPIO4 interrupt.  
4
(Trigger controlled by GP4 registers.)  
Note: This bit is cleared once read.  
GPIO3interrupt.  
3
(Trigger controlled by GP3 registers.)  
Note: This bit is cleared once read.  
GPIO2 interrupt.  
2
(Trigger controlled by GP2 registers.)  
Note: This bit is cleared once read.  
GPIO1 interrupt.  
1
(Trigger controlled by GP1 registers.)  
Note: This bit is cleared once read.  
GPIO0 interrupt.  
0
(Trigger controlled by GP0 registers.)  
Note: This bit is cleared once read.  
Register 1Eh GPIO Interrupt Status  
PD, February 2011, Rev 4.4  
235  
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