欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8352 参数 Datasheet PDF下载

WM8352图片预览
型号: WM8352
PDF下载: 下载PDF文件 查看货源
内容描述: 欧胜音频Plusa ? ¢立体声CODEC与电源管理 [Wolfson AudioPlus™ Stereo CODEC with Power Management]
分类和应用:
文件页数/大小: 336 页 / 2353 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8352的Datasheet PDF文件第229页浏览型号WM8352的Datasheet PDF文件第230页浏览型号WM8352的Datasheet PDF文件第231页浏览型号WM8352的Datasheet PDF文件第232页浏览型号WM8352的Datasheet PDF文件第234页浏览型号WM8352的Datasheet PDF文件第235页浏览型号WM8352的Datasheet PDF文件第236页浏览型号WM8352的Datasheet PDF文件第237页  
Production Data  
WM8352  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
RTC periodic interrupt.  
REFER TO  
7
6
5
2
1
0
RTC_PER_EINT  
0
(Rising Edge triggered)  
Note: This bit is cleared once read.  
RTC 1s rollover complete (1Hz tick).  
(Rising Edge triggered)  
RTC_SEC_EINT  
RTC_ALM_EINT  
0
0
0
0
0
Note: This bit is cleared once read.  
RTC alarm signalled.  
(Rising Edge triggered)  
Note: This bit is cleared once read.  
Battery Voltage < 3.9 interrupt.  
(Rising Edge triggered)  
CHG_VBATT_LT_3P9_EINT  
CHG_VBATT_LT_3P1_EINT  
CHG_VBATT_LT_2P85_EINT  
Note: This bit is cleared once read.  
Battery voltage < 3.1 interrupt.  
(Rising Edge triggered)  
Note: This bit is cleared once read.  
Battery voltage < 2.85 interrupt.  
(Rising Edge triggered)  
Note: This bit is cleared once read.  
Register 19h Interrupt Status 1  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
R26 (1Ah)  
Interrupt  
Status 2  
13  
CS1_EINT  
0
Flag to indicate drain voltage can no  
longer be regulated and output current  
may be out of spec.  
(Rising Edge triggered)  
Note: This bit is cleared once read.  
12  
CS2_EINT  
0
Flag to indicate drain voltage can no  
longer be regulated and output current  
may be out of spec.  
(Rising Edge triggered)  
Note: This bit is cleared once read.  
USB limit switch interrupt.  
(Rising Edge triggered)  
10  
8
USB_LIMIT_EINT  
0
0
0
0
0
0
Note: This bit is cleared once read.  
Auxiliary data ready.  
AUXADC_DATARDY_EINT  
AUXADC_DCOMP4_EINT  
AUXADC_DCOMP3_EINT  
AUXADC_DCOMP2_EINT  
AUXADC_DCOMP1_EINT  
(Rising Edge triggered)  
Note: This bit is cleared once read.  
DCOMP4 interrupt.  
7
(Rising Edge triggered)  
Note: This bit is cleared once read.  
DCOMP3 interrupt.  
6
(Rising Edge triggered)  
Note: This bit is cleared once read.  
DCOMP2 interrupt.  
5
(Rising Edge triggered)  
Note: This bit is cleared once read.  
DCOMP1 interrupt.  
4
(Rising Edge triggered)  
Note: This bit is cleared once read.  
PD, February 2011, Rev 4.4  
233  
w
 复制成功!