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WM8321GEFL/RV 参数 Datasheet PDF下载

WM8321GEFL/RV图片预览
型号: WM8321GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 处理器电源管理子系统 [Processor Power Management Subsystem]
分类和应用:
文件页数/大小: 253 页 / 1578 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8321  
DC-DC Converters 1 and 2 support two different switching frequencies, as described in Section 15.6.  
Note that the supported output voltage range for these converters is restricted in the 4MHz mode; for  
output voltages greater than 1.4V, the 2MHz mode must be used.  
The DC-DC Converters are dynamically programmable - the output voltage may be adjusted in  
software at any time. These converters are step-down converters; their output voltage can therefore  
be lower than the input voltage, but cannot be higher.  
Note that the output voltage of DC-DC Converters 1 and 2 may also be controlled using the Dynamic  
Voltage Scaling features described in Section 15.6. Software control (using register writes) and  
hardware control (using the Hardware DVS Control inputs supported via GPIO) is supported.  
Note that the output voltage of the DC-DC Converters may also be controlled by the Hardware  
Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See  
Section 15.8 for details of Hardware Control.  
When changing the output voltage of DC-DC Converters 1 and 2, the GPIO output “DC-DCm DVS  
Done” can be used to confirm the DVS Control has completed; see Section 15.6 for details.  
15.5.2 LDO REGULATORS 1-10  
The output voltage of the LDO Regulators 1-10 in the ON power state is selected using the  
LDOn_ON_VSEL register fields. The output voltage of the LDO Regulators in the SLEEP power state  
is selected using the LDOn_SLP_VSEL register fields.  
The LDO Regulators are dynamically programmable - the output voltage may be adjusted in software  
at any time.  
Note that the output voltage of the LDO Regulators may also be controlled by the Hardware Control  
inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.8 for  
details of Hardware Control.  
15.5.3 LDO REGULATOR 11  
The output voltage of LDO11 can be set in two ways - it can be commanded directly, or it can be  
commanded to follow the DC-DC Converter 1 output voltage.  
When LDO11_VSEL_SRC = 0, then the output voltage of LDO11 is set by LDO11_ON_VSEL (in the  
ON state) or by LDO11_SLP_VSEL (in the SLEEP state) in the same way as the other LDOs.  
When LDO11_VSEL_SRC = 1, the output voltage of LDO11 follows the output voltage of DC-DC  
Converter 1. This enables both domains to be changed at the same time, eg. the processor core and  
processor ‘alive’ domains. In this case, the LDO11 output voltage follows DC1_ON_VSEL or  
DC1_SLP_VSEL in the ON state or SLEEP state respectively.  
Note that, when LDO11_VSEL_SRC = 1, the LDO11 regulator adopts the nearest achievable output  
voltage, which may not be identical to the DC-DC1 voltage, due to the more limited range and  
resolution of LDO11 - the output voltage of LDO11 is in the range 0.8V to 1.55V in 50mV steps; the  
output voltage of DC-DC1 is in the range 0.6V to 1.8V in 12.5mV steps. If DC-DC1 is disabled, then  
the LDO11 voltage tracking feature is not supported, and the LDO11 output voltage will be 0.8V.  
15.6 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL  
Soft-Start control is provided for each of the DC-DC synchronous buck converters, using the  
DCm_SOFT_START register fields. When a DC-DC Converter is switched on, the soft-start circuit will  
apply current limiting in order to control the in-rush current. For DC-DC1 and DC-DC2, the current  
limit is increased through up to 8 stages to the full load condition. The DCm_SOFT_START registers  
select the duration of these stages. (Note that, under light loads, the full start-up may be achieved in  
fewer than 8 stages.) A similar function is provided for DC-DC3 and DC-DC4, but only 3 intermediate  
stages are implemented for these converters.  
When DC-DC3 or DC-DC4 is operating in Hysteretic Mode, the maximum DC output current can be  
set using the DC3_STNBY_LIM and DC4_STNBY_LIM registers. See Section 15.4.1 for details of the  
DC-DC3 and DC-DC4 operating modes.  
PD, February 2012, Rev 4.0  
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