WM8321
Production Data
15 POWER MANAGEMENT
15.1 GENERAL DESCRIPTION
The WM8321 provides 4 DC-DC synchronous buck converters and 11 LDO regulators. The regulators
comprise general purpose LDOs (LDO1 - LDO6) and low-noise analogue LDOs (LDO7 - LDO10). The
analogue LDOs offer superior PSRR, noise and load-transient performance. LDO11 is a low power
LDO intended for powering “always on” circuits connected to the WM8321; this LDO can be
configured to remain enabled in the OFF state.
These power management components are designed to support application processors and
associated peripherals. DC-DC1 and DC-DC2 are intended to provide power to the processor voltage
domains; DC-DC3 is suitable for powering memory circuits or for use as a pre-regulator for the LDOs.
The output voltage of each of the buck converters and regulators is programmable in software
through control registers. DC-DC3 and DC-DC4 can be ganged together in dual mode, providing an
increased current capability for higher power processor voltage domains.
The WM8321 can execute programmable sequences of enabling and disabling the DC-DC
Converters and LDO Regulators as part of the transitions between the ON, OFF and SLEEP power
states. The WM8321 power management circuits can also interface with configurable hardware
control functions supported via GPIO pins. These include GPIO inputs for selecting alternate voltages
or operating modes, and GPIO outputs for controlling external power management circuits.
The configuration of the power management circuits, together with some of the GPIO pins and other
functions, may be stored in the integrated OTP memory. This avoids any dependence on a host
processor to configure the WM8321 at start-up. See Section 14 for details of the OTP memory.
15.2 DC-DC CONVERTER AND LDO REGULATOR ENABLE
The integrated DC-DC Converters and LDO Regulators can each be enabled in the ON or SLEEP
power states by setting the DCm_ENA or LDOn_ENA bits as defined in Section 15.11.1. Note that
setting the DCm_ENA or LDOn_ENA bits in the OFF state will not enable the DC-DC Converters or
LDO Regulators. These bits should not be written to when the WM8321 is in the OFF state; writing to
these bits in the OFF state may cause a malfunction.
In many applications, there will be no need to write to the DCm_ENA or LDOn_ENA bits, as these bits
are controlled by the WM8321 when a power state transition is scheduled. Dynamic, run-time control
of the DC-DC Converters or LDO Regulators is also possible by writing to these registers.
The DC-DC Converters and LDO Regulators can be assigned to a Hardware Enable (GPIO) input for
external enable/disable control. In this case, the converter or regulator is not affected by the
associated DCm_ENA or LDOn_ENA bits. See Section 15.3 for further details.
The WM8321 can also control other circuits, including external DC-DC Converters or LDO Regulators
using the External Power Enable (EPE) outputs. The External Power Enable outputs are alternate
functions supported via GPIO - see Section 21. The External Power Enable outputs can be controlled
in the same way as the internal DC-DC Converters and LDO Regulators. The associated control bits
are EPE1_ENA and EPE2_ENA, as defined in Section 15.11.1.
LDO Regulator 11 is a Low Power LDO Regulator, which is configured differently to the other LDOs. It
is a low-power LDO intended for “Always-On” functions external to the WM8321 and can be enabled
when the WM8321 is in the OFF power state.
When LDO11_FRCENA is set, then LDO11 is enabled at all times in the OFF, ON and SLEEP states.
Note that LDO11 is always disabled in the BACKUP and NO POWER states. See Section 15.11.3 for
the definition of LDO11_FRCENA.
The current commanded state of each of the DC-DC Converters, LDO Regulators and EPE outputs is
indicated in the DCm_STS, LDOn_STS and EPEn_STS register bits.
If a fault condition causes any converter or regulator to be disabled, then the associated _ENA and
_STS fields are reset to 0.
PD, February 2012, Rev 4.0
62
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
