Production Data
WM8321
REGISTER
ADDRESS
BIT
LABEL
GP9_LVL
DEFAULT
DESCRIPTION
REFER TO
GPIO9 level.
8
0
When GP9_FN = 0h and GP9_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP9_POL is 0, the register contains the opposite
logic level to the external pin.
GP8_LVL
GP7_LVL
GP6_LVL
GP5_LVL
GP4_LVL
GP3_LVL
GP2_LVL
GP1_LVL
GPIO8 level.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
When GP8_FN = 0h and GP8_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP8_POL is 0, the register contains the opposite
logic level to the external pin.
GPIO7 level.
When GP7_FN = 0h and GP7_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP7_POL is 0, the register contains the opposite
logic level to the external pin.
GPIO6 level.
When GP6_FN = 0h and GP6_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP6_POL is 0, the register contains the opposite
logic level to the external pin.
GPIO5 level.
When GP5_FN = 0h and GP5_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP5_POL is 0, the register contains the opposite
logic level to the external pin.
GPIO4 level.
When GP4_FN = 0h and GP4_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP4_POL is 0, the register contains the opposite
logic level to the external pin.
GPIO3 level.
When GP3_FN = 0h and GP3_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP3_POL is 0, the register contains the opposite
logic level to the external pin.
GPIO2 level.
When GP2_FN = 0h and GP2_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP2_POL is 0, the register contains the opposite
logic level to the external pin.
GPIO1 level.
When GP1_FN = 0h and GP1_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP1_POL is 0, the register contains the opposite
logic level to the external pin.
Register 400Ch GPIO Level
PD, February 2012, Rev 4.0
151
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
