WM8321
Production Data
Note that GPIO input functions 2h, 3h, 4h, 5h and 6h are edge-triggered only. The associated state
transition(s) are scheduled only when a rising or falling edge is detected on the respective GPIO pin.
At other times, it is possible that other state transition events may cause a state transition regardless
of the state of the GPIO input. See Section 11.3 for details of all the state transition events.
21.4 GPIO INTERRUPTS
Each GPIO pin has an associated interrupt flag, GPn_EINT, in Register R16405 (4015h). Each of
these secondary interrupts triggers a primary GPIO Interrupt, GP_INT (see Section 23). This can be
masked by setting the mask bit(s) as described in Table 58.
See Section 28 and Section 29 for a definition of the register bit positions applicable to each GPIO.
ADDRESS
R16405
BIT
LABEL
GPn_EINT
DESCRIPTION
GPIO interrupt.
15:0
(4015h)
(Trigger is controlled by GPn_INT_MODE)
Interrupt Status
5
Note: Cleared when a ‘1’ is written.
R16413
(401Dh)
IM_GPn_EINT
Interrupt mask.
15:0
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
5 Mask
Default value is 1 (masked)
Note: n is a number between 1 and 12 that identifies the individual GPIO.
Table 58 GPIO Interrupts
PD, February 2012, Rev 4.0
114
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
